Jason Dunlap has over 25 years of experience designing PC boards; all our designers have more than 10 years experience. Most digital designs do not present difficult problems or very many critical issues until you get into high frequency buses and fast clock speeds. We’ve done designs with 900MHz and 2.5GHz busses, multiple clocks with different clock speeds to over 300MHz. It is at these speeds that controlled impedance, and matched lengths between buses and clocks become critical.
The most difficult design issues arise when high frequency analog circuits must interface to high frequency digital circuits, as in the PC board shown here. This design had an optical coupled analog front end that is fed into 4 QDR BGAs. From there, 128 differential pairs had to be matched length, and were routed into the BGA. The output was impedance controlled, differential pairs that routed to the PCI Express connector.
High Density designs also present some special problems. Component placement becomes very critical in order to get a high number of components into a small area and still be able to route all the connections. Sometimes blind and buried vias are unavoidable. We try to minimize this by test routing of critical traces, and careful analysis of the design.
The board shown here was quite dense, having many components on both sides of the board. There were a multitude of different power supply voltages, which complicated matters because not only was layer count limited, there were many impedance controlled nets that could not pass over splits in the power plane layers. These are the kind of challenges our designers deal with all the time.
